1. Field of the Invention
The invention relates to an MOS transistor having an extended charge carrier drift zone between the gate and drain to achieve high reverse breakdown voltage, and particularly to such a transistor having a closed layout plan wherein the drain is laterally surrounded by the source and the gate so that a high voltage connection bus for the drain must traverse a path which crosses the drift zone. The term "MOS transistor" as used herein refers to a field effect transistor having a source, a drain and a gate, the gate electrode extending over a dielectric layer, for example silicon oxide or nitride, at the surface of the transistor; the gate electrode when energized causing either enhancement or depletion of charge carriers in an underlying surface channel of the transistor which constitutes the gate between the source and the drain. 2. Description of the Related Art
There is an increasing need for MOS integrated circuits which can sustain high reverse breakdown voltages. That is, wherein the drains of one or more MOS transistors therein may be subjected to voltages of the order of several hundred volts relative to the source. U.S. Pat. No. 4,300,150, issued Nov. 10, 1981, assigned to the present assignee, discloses a double-diffused MOS transistor (DMOS) wherein high reverse breakdown voltage is achieved by providing an extended charge carrier drift zone in an epitaxial layer between the gate and drain in order to provide a gradual distribution of the drain potential over the length of the drift zone. However, in order to minimize the area of such a transistor on an IC chip, it is advantageous to employ a closed layout plan wherein the source and gate are at the periphery and surround the drain. Consequently, in order for a high voltage external connection bus to reach the drain, it must extend over the drift zone between the gate and drain. The electric field produced by the bus will therefore influence the flow of charge carriers in the drift zone, and unless adequately shielded will degrade the operation of the transistor.
The article "400V MOS IC For EL Display" by K. Fujii et al, p. 46-47, 1981 IEEE International Solid State Circuits Conference, describes an MOS transistor having an extended drift zone and a closed layout plan in which the drain is surrounded by the source and gate at the periphery of the layout. A pair of layers of concentric annular field plates which are unconnected ("floating" in potential) are provided between the gate and drain to reduce enhancement of the electric field produced in the drift zone by the field plates, thereby avoiding reduction of the reverse breakdown voltage of the transistor due to such electric field. However, the article does not address the problem of how a high voltage connection bus can be extended to the drain without the electric field therefrom effecting the drift zone.
The article "850V NMOS Driver With Active Outputs" by R. Martin et al, 1984 IEDM, p. 266-269, also describes a high voltage MOS transistor with an extended drift zone and having a closed layout plan. A double layer of successive polysilicon field plates extends across the drift zone, the upper layer of the field plates being described as serving to shield the substrate from the field potential of a high voltage bus. However, there is no description of how to extend the connection bus across the gate and source electrodes or of how to further improve the shielding of the drift zone.